The present invention relates to an analogue to digital converter.
High speed and high resolution are highly desirable features when designing analogue to digital converters (ADCs). The latest ADCs are the 12 bit 65 MS/s level converters, one example of which is Philips model TDA 8767/8. It is desirable to achieve 14 bit or higher accuracy.
One known approach to achieving high speed and high resolution is to use calibration, i.e. to store non-linearity information and digitally correct the ADC on-line. This requires large amounts of digital and memory circuitry and also the ADC must be off-line while the calibration signal is generated and this is undesirable.
Another approach is to use a ladder resistor combined with offset compensated amplifiers in a two or three step 14 bit ADC. Problems arise in realizing ladder resistors accurately and the noise levels tend to be higher than desirable.
Yet a further approach is to use the static linearity of a current DAC (digital to analogue converter). For example, a known such implementation comprises:
a sample and hold circuit;
a coarse analogue to digital converter (ADC);
a digital to analogue converter (DAC);
combining logic circuitry; and
a fine analogue to digital converter (ADC).
This is a known as basic pipeline/subranging architecture. However, major problems arise in matching the DAC with the inter-stage gain and with the range of fine ADCs and offsets and the speed and resolution of known implementations have been limited.
The present invention aims to provide an ADC with high speed and high resolution without the disadvantages of the known implementations described above.
According to the present invention there is provided a circuit for analogue to digital conversion comprising;
a sample and hold circuit;
a coarse analogue to digital converter;
a digital to analogue converter;
combining logic circuitry;
a fine analogue to digital converter; characterized by
a voltage to current converter (R1);
means for subtracting in the current domain;
means for summing at a virtual earth node; and
means for converting current to voltage at the input to the fine analogue to digital converter.
According to a preferred embodiment the subtracting means comprises a current digital to analogue converter and preferably a matched unit current cell.
Preferably the fine analogue to digital converter additionally comprises a resistor matched to the means for converting current to voltage, and a current source matched to the current of the digital to analogue converter current cells.
According to a further aspect of the invention there is provided a plurality of pairs of voltage to current and current to voltage converters connected in cascade formation. Hence the ladder of the second ADC will only approximately determine the range and the second ADC and will drive another series of matched current sources.
According to a preferred embodiment of the further aspect of the invention, a plurality of sample and hold circuits are provided. This has the advantage of increasing the sample rate of the circuit.
An implementation according to the invention, enables a reduction in the number of components to be matched is reduced and the level of matching is reduced to the subrange accuracy.